Random access memories, such as static random access memories (SRAMs) or dynamic random access memories (DRAMs), generally comprise a multiplicity of addresses for writing therein data. FIG. 1 illustrates a demonstrative example of an SRAM 10. SRAM 10 may include, for purposes of example only and without limitation to these values, 66 addresses 12, each of which may store 64 bit words designated DATA(63,0). Data in the addresses may be accessed through data latches 14 for performing operations, e.g., programming, on a memory cell array (not shown). In the illustrated example, 64 data latches would be required.
Memory cell array may comprise non-volatile memory (NVM) cells, which store bits that may be programmed with program pulses. A “program pulse” is a set of voltages selected to bring the particular bit to a programmed state. A single programmed pulse may be insufficient to bring the bit to a programmed state. Moreover, in some cases, “leaping” to a programmed state with a single programming pulse may have adverse effects on functional reliability of the NVM cell. Accordingly, a plurality of programming pulses may be applied to program the bits of the NVM cells. However, this may pose a different problem with regard to accessing data from the SRAM 10, as is now explained.
In order to apply program pulses to the cells of the array, data is first retrieved from the SRAM 10. After each programming pulse applied to the array, “program verification” is performed, meaning that the bits are verified to check if they have attained a programmed state. Program verification also involves interrogation of the SRAM 10 in order to check which bits must be further programmed. Thus, a program cycle of, for example, 3 programming pulses, requires 6 passes over the entire SRAM. For the illustrated example that has 66 addresses, if the SRAM clock cycle is 50 nanoseconds (a typical value), then the total time spent on retrieving and writing=66×50 nsec×6=19.8 microseconds. This is a relatively long time and hampers performance of the SRAM 10 and array.
One known solution to speeding up the performance of the SRAM involves “look ahead”, and is described with reference to FIG. 2. The method is based on the likelihood that not every address may comprise data that needs to be programmed in array. Valuable time may be saved if those addresses that do not require programming were to be skipped, thereby saving the double retrieve of data from SRAM 10. Accordingly, the method “looks ahead”, i.e., searches, for the next data to be programmed while the previous data is being programmed. This may be accomplished with various control hardware and software. As seen in FIG. 2, the hardware may comprise address latches (or FFs) 18 and internal address control circuitry 20. In the illustrated example, since there are 66 addresses, which may be represented by 7 bits, 7 address FFs 18 are required.
The solution of FIG. 2 has several disadvantages. First, the additional hardware occupies valuable component space. Second, the look ahead search must be synchronized with the programming that is currently being performed, thereby complicating the control process. Third, the method only looks ahead in program, but not read.